A metal oxide thin-film transistor (TFT) is a basic circuit component that may be widely used in various electronic systems, and it has many advantages, such as high electron mobility, a low-temperature manufacturing process, relatively high stability, and high transparency. As shown in FIG. 1, in a conventional TFT manufacturing process, an alignment between a gate (Gate) 101 and a source (Source) 102 or a drain (Drain) 103 that are of the TFT component is implemented by using two layers of different mask plates and in a manual or mechanical optical alignment manner. Restricted by factors such as precision of an alignment device, this manner results in that the source 102 and the drain 103 overlap the gate 101, thereby causing relatively large gate-source parasitic capacitance (Cgs) and gate-drain parasitic capacitance (Cgd). The relatively large parasitic capacitance generally reduces a cut-off frequency of the component (a cut-off frequency is in an inverse proportion to parasitic capacitance), thereby reducing a running speed of a circuit; in addition, the relatively large parasitic capacitance also causes that voltage of a display electrode departs from a design requirement, so that a complicated gate drive circuit is required to compensate a deviation, which increases complexity of a circuit design; in addition, parasitic capacitance that cannot be precisely controlled also increase complexity and uncertainty of the circuit design, and a minimum size of a channel (Channel) cannot be precisely controlled, thereby limiting size minimization of the channel, and making it difficult to improve performance of the component. In addition, use of a multilayer mask plate in a conventional component also increases process complexity and costs, which is unfavorable to improvement of production efficiency.
To resolve the foregoing problems, the prior art proposes a self-aligned component that is designed by using a specified process and may automatically align the source and the drain with the gate in a manufacturing process, and there is no need to align two layers of different mask plates in a manual manner or through mechanical optics, an alignment between the source or the drain and the gate may be implemented. This type of self-aligned component is widely applied to a conventional monocrystalline silicon chip (MOSFET) manufacturing process; however, a self-aligned process of the transistor in the conventional silicon chip cannot be directly applied to the metal oxide TFT.
To resolve this problem, a self-aligned process is proposed in the prior art, in which a top gate is used as a mask, an automatic alignment is performed to form the source and the drain, Ar plasma, or NH3 plasma that has more hydrogen is used to process a surface of the metal oxide of indium gallium zinc oxide (IGZO), so as to reduce contact resistance of the source and the drain region. However, the Ar plasma only partially improves surface resistance of a source area, a drain area and a metal contact, but resistance of the source area and the drain area is still large, and the plasma needs additional technological processing, which increases costs; the hydrogen can spread to the channel, which degrades the device reliability and causes that the source area and the drain area are extended to the channel, an overlapped area of the gate and the source and an overlapped area of the gate and the drain increase, and parasitic capacitance increases, thereby reducing performance of the metal oxide TFT component.
In another existing self-aligned process, for example, the Chinese Patent Application No. CN201080017247, an etch-stop layer needs to be formed on a semiconductor layer; the etch-stop layer, a source and a drain are separately formed through two times of exposure, so that two times of back exposure and self-alignment increase use of a photolithographic mask and greatly increase difficulty in implementing the process. In addition, the etch-stop layer also produces an adverse effect on a semiconductor channel, thereby affecting an electrical property of a TFT.
For another example, the Chinese Patent Application No. CN201110147134 discloses a TFT manufacturing process, in which a grey-tone mask is used. By changing exposure, one set of mask plate is used to separately implement preparation of a source, a drain, and a semiconductor channel. However, a size of the channel is strictly restricted by specifications of the mask aligner, and the exposure needs to be relatively precisely controlled to distinguish the source and the drain from the semiconductor channel, so that the TFT manufacturing process is subject to a relatively large restriction and is relatively difficult to be applied, and in addition, which is unfavorable to reduction of preparation costs.